Unums (universal numbers[1]) are a family of number formats and arithmetic for implementing real numbers on a computer, proposed by John L. Gustafson in 2015.[2] They are designed as an alternative to the ubiquitous IEEE 754 floating-point standard. The latest version is known as posits.[3]
Type I Unum
The first version of unums, formally known as Type I unum, was introduced in Gustafson's book The End of Error as a superset of the IEEE-754 floating-point format.[2] The defining features of the Type I unum format are:
a u-bit, which determines whether the unum corresponds to an exact number (u = 0), or an interval between consecutive exact unums (u = 1). In this way, the unums cover the entire extended real number line [−∞,+∞].
For computation with the format, Gustafson proposed using interval arithmetic with a pair of unums, what he called a ubound, providing the guarantee that the resulting interval contains the exact solution.
Type II Unums were introduced in 2016[8] as a redesign of Unums that broke IEEE-754 compatibility : in addition to the sign bit and the interval bit mentioned earlier, the Type II unum uses a bit to indicate inversion. These three operations make it possible, starting from a finite set of points between one and infinity, to quantify the entire projective line except for four points: the two exceptions, 0 and ∞, and then 1 and -1. This set of points is chosen arbitrarily, and arithmetic operations involving them are not performed logically but rather by using a lookup table. The size of such a table becomes prohibitive for an encoding format spanning multiple bytes. This challenge necessitated the development of the Type III unum, known as the posit, discussed below.
Posit (Type III Unum)
In February 2017, Gustafson officially introduced Type III unums (posits), for fixed floating-point-like values and valids for interval arithmetic.[3] In March 2022, a standard was ratified and published by the Posit Working Group.[9]
Posits[3][10][11] are a hardware-friendly version of unum where difficulties faced in the original type I unum due to its variable size are resolved. Compared to IEEE 754 floats of similar size, posits offer a bigger dynamic range and more fraction bits for values with magnitude near 1 (but fewer fraction bits for very large or very small values), and Gustafson claims that they offer better accuracy.[12][13] Studies[14][15] confirm that for some applications, posits with quire out-perform floats in accuracy. Posits have superior accuracy in the range near one, where most computations occur. This makes it very attractive to the current trend in deep learning to minimize the number of bits used. It potentially helps any application to accelerate by enabling the use of fewer bits (since it has more fraction bits for accuracy) reducing network and memory bandwidth and power requirements.
The format of an n-bit posit is given a label of "posit" followed by the decimal digits of n (e.g., the 16-bit posit format is "posit16") and consists of four sequential fields:
regime: at least 2 bits and up to (n − 1), representing an unsigned integer r as described below
exponent: generally 2 bits as available after regime, representing an unsigned integer e
fraction: all remaining bits available after exponent, representing a non-negative real dyadic rationalf less than 1
The regime field uses unary coding of k identical bits, followed by a bit of opposite value if any remaining bits are available, to represent an unsigned integer r that is −k if the first bit is 0 or k − 1 if the first bit is 1. The sign, exponent, and fraction fields are analogous to IEEE 754 sign, exponent, and significand fields (respectively), except that the posit exponent and fraction fields may be absent or truncated and implicitly extended with zeroes—an absent exponent is treated as 002 (representing 0), a one-bit exponent E1 is treated as E102 (representing the integer 0 if E1 is 0 or 2 if E1 is 1), and an absent fraction is treated as 0. Negative numbers (s is 1) are encoded as 2's complements.
The two encodings in which all non-sign bits are 0 have special interpretations:
If the sign bit is 1, the posit value is NaR ("not a real")
If the sign bit is 0, the posit value is 0 (which is unsigned and the only value for which the sign function returns 0)
Otherwise, the posit value is equal to , in which r scales by powers of 16, e scales by powers of 2, f distributes values uniformly between adjacent combinations of (r, e), and s adjusts the sign symmetrically about 0.
Examples
type (positn)
Binary
Value
Notes
Any
10…
NaR
anything not mathematically definable as a unique real number[9]
Any
00…
0
Any
010…
1
Any
110…
−1
Any
00111 0…
0.5
Any
00…1
smallest positive value
Any
01…
largest positive value
posit8
00000001
smallest positive value
posit8
01111111
largest positive value
posit16
0000000000000001
smallest positive value
posit16
0111111111111111
largest positive value
posit32
00000000000000000000000000000001
smallest positive value
posit32
01111111111111111111111111111111
largest positive value
Note: 32-bit posit is expected to be sufficient to solve almost all classes of applications[citation needed].
Quire
For each positn type of precision , the standard defines a corresponding "quire" type quiren of precision , used to accumulate exact sums of products of those posits without rounding or overflow in dot products for vectors of up to 231 or more elements (the exact limit is ). The quire format is a two's complement signed integer, interpreted as a multiple of units of magnitude except for the special value with a leading sign bit of 1 and all other bits equal to 0 (which represents NaR). Quires are based on the work of Ulrich W. Kulisch and Willard L. Miranker.[16]
Valid
Valids are described as a Type III Unum mode that bounds results in a given range.[3]
Implementations
Several software and hardware solutions implement posits.[14][17][18][19][20] The first complete parameterized posit arithmetic hardware generator was proposed in 2018.[21]
Unum implementations have been explored in Julia[22][23][24][25][26][27] and MATLAB.[28][29] A C++ version[30] with support for any posit sizes combined with any number of exponent bits is available. A fast implementation in C, SoftPosit,[31] provided by the NGA research team based on Berkeley SoftFloat adds to the available software implementations.
Open source (MIT license). Original definition and prototype. Most complete environment for comparing IEEE floats and posits. Many examples of use, including linear solvers
Leverages Julia's templated mathematics standard library, can natively do matrix and tensor operations, complex numbers, FFT, DiffEQ. Support for valids
Intended for Deep Learning applications Addition, Subtraction and Multiplication only. A proof of concept matrix multiplier has been built, but is off-spec in its precision
Open-Source Posit RISC-V Core with Quire Capability
Posit<32,2> with 512-bit quire
Yes
Speed of design is based on the underlying hardware platform (ASIC/FPGA)
Functionality testing of each posit instruction.
Application-level posit-capable RISC-V core based on CVA6 that can execute all posit instructions, including the quire fused operations. PERCIVAL is the first work that integrates the complete posit ISA and quire in hardware. It allows the native execution of posit instructions as well as the standard floating-point ones simultaneously.
World's first posit-enabled ASIC with octa-core RISC-V processor and Quire implemented.
PCIe accelerator card with this silicon will be ready June 2024
Fully software stack with compilers, debugger, IDE environment and math libraries for applications. C, C++, Python languages supported
Applications tested successfully - image and video compression, more to come
<32, 2> with Quire 512 bits support.
<64, 3>
Yes - Fully supported.
500 MHz * 8 Cores
Exhaustive tests completed for 32 bits and 64 bits with Quire support completed.
Applications tested and being made available for seamless adoption
www.calligotech.com
Fully integrated with C/C++ types and automatic conversions. Supports full C++ math library (native and conversion to/from IEEE). Runtime integrations: GNU Utils, OpenBLAS, CBLAS. Application integrations: in progress. Compiler support extended: C/C++, G++, GFortran & LLVM (in progress).
80 MPOPS for div32/2 and similar linear functions. Much higher for truncate and much lower for exp.
Fuzzing against C softposit with a lot of iterations for 16/1 and 32/2. Explicitly testing edge cases found.
(MIT license) The implementations where ES is constant the code is generated. The generator should be able to generate for all sizes {8,16,32} and ES below the size. However, the ones not included into the library by default are not tested, fuzzed, or supported. For some operations on 32/ES, mixing and matching ES is possible. However, this is not tested.
SoftPosit
SoftPosit[31] is a software implementation of posits based on Berkeley SoftFloat.[32] It allows software comparison between posits and floats. It currently supports
Add
Subtract
Multiply
Divide
Fused-multiply-add
Fused-dot-product (with quire)
Square root
Convert posit to signed and unsigned integer
Convert signed and unsigned integer to posit
Convert posit to another posit size
Less than, equal, less than equal comparison
Round to nearest integer
Helper functions
convert double to posit
convert posit to double
cast unsigned integer to posit
It works for 16-bit posits with one exponent bit and 8-bit posit with zero exponent bit. Support for 32-bit posits and flexible type (2-32 bits with two exponent bits) is pending validation. It supports x86_64 systems. It has been tested on GNU gcc (SUSE Linux) 4.8.5 Apple LLVM version 9.1.0 (clang-902.0.39.2).
Examples
Add with posit8_t
#include"softposit.h"intmain(intargc,char*argv[]){posit8_tpA,pB,pZ;pA=castP8(0xF2);pB=castP8(0x23);pZ=p8_add(pA,pB);// To check answer by converting it to doubledoubledZ=convertP8ToDouble(pZ);printf("dZ: %.15f\n",dZ);// To print result in binary (warning: non-portable code)uint8_tuiZ=castUI8(pZ);printBinary((uint64_t*)&uiZ,8);return0;}
Fused dot product with quire16_t
// Convert double to positposit16_tpA=convertDoubleToP16(1.02783203125);posit16_tpB=convertDoubleToP16(0.987060546875);posit16_tpC=convertDoubleToP16(0.4998779296875);posit16_tpD=convertDoubleToP16(0.8797607421875);quire16_tqZ;// Set quire to 0qZ=q16_clr(qZ);// Accumulate products without roundingsqZ=q16_fdp_add(qZ,pA,pB);qZ=q16_fdp_add(qZ,pC,pD);// Convert back to positposit16_tpZ=q16_to_p16(qZ);// To check answerdoubledZ=convertP16ToDouble(pZ);
Critique
William M. Kahan, the principal architect of IEEE 754-1985 criticizes type I unums on the following grounds (some are addressed in type II and type III standards):[6][33]
The description of unums sidesteps using calculus for solving physics problems.
Unums can be expensive in terms of time and power consumption.
Each computation in unum space is likely to change the bit length of the structure. This requires either unpacking them into a fixed-size space, or data allocation, deallocation, and garbage collection during unum operations, similar to the issues for dealing with variable-length records in mass storage.
Unums provide only two kinds of numerical exception, quiet and signaling NaN (Not-a-Number).
Unum computation may deliver overly loose bounds from the selection of an algebraically correct but numerically unstable algorithm.
^Tichy, Walter F. (September 2016). "Unums 2.0: An Interview with John L. Gustafson". Ubiquity.ACM.org. Retrieved 2017-01-30. I started out calling them "unums 2.0," which seemed to be as good a name for the concept as any, but it is really not a "latest release" so much as it is an alternative.
^John L. Gustafson and I. Yonemoto. (February 2017) Beyond Floating Point: Next Generation Computer Arithmetic. [Online]. Available: https://www.youtube.com/watch?v=aP0Y1uAA-2Y
^ abLindstrom, Peter; Lloyd, Scott; Hittinger, Jeffrey (March 2018). Universal Coding of the Reals: Alternatives to IEEE Floating Point. Conference for Next Generation Arithmetic. Art. 5. ACM. doi:10.1145/3190339.3190344.
^David Mallasén; Alberto A. Del Barrio; Manuel Prieto-Matias (2024). "Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing". IEEE Transactions on Computers. 73 (6): 1472–1485. arXiv:2305.06946. doi:10.1109/TC.2024.3377890.
^S. Chung, "Provably Correct Posit Arithmetic with Fixed-Point Big Integer." ACM, 2018.
^J. Chen, Z. Al-Ars, and H. Hofstee, "A Matrix-Multiply Unit for Posits in Reconfigurable Logic Using (Open)CAPI." ACM, 2018.
^Z. Lehoczky, A. Szabo, and B. Farkas, "High-level .NET Software Implementations of Unum Type I and Posit with Simultaneous FPGA Implementation Using Hastlayer." ACM, 2018.
^S. Langroudi, T. Pandit, and D. Kudithipudi, "Deep Learning Inference on Embedded Devices: Fixed-Point vs Posit". In Energy Efficiency Machine Learning and Cognitive Computing for Embedded Applications (EMC), 2018. [Online]. Available: https://sites.google.com/view/asplos-emc2/program
Sterbenz, Pat H. (1974-05-01). Floating-Point Computation. Prentice-Hall Series in Automatic Computation (1st ed.). Englewood Cliffs, New Jersey, USA: Prentice Hall. ISBN0-13-322495-3.